VHDL ON XILINX Version 12.4

VHDL ON XILINX Version 12.4

If one is familiar with digital hardware design and worked with any programming language then Learning VHDL is quite easy. In this content I will cover the basics of VHDL language, programming concepts and working with Xilinx 12.4 version. With this brief let us starts learning from the very basic.

VHDL Stands for

•      V- VHSIC

–     Very High Speed Integrated Circuit

•      H- Hardware

•      D- Description

•      L- Language

Why Use VHDL?

•      Quick Time-to-Market

–     Allows designers to quickly develop designs requiring tens of thousands of logic gates.

–     Provides powerful high-level constructs for describing complex logic.

–     Supports modular design methodology and multiple levels of hierarchy.

•      One language for design and simulation.

•      Allows creation of device-independent designs that are portable to multiple vendors. Good for ASIC Migration.

•      Allows user to pick any synthesis tool, vendor, or device.

BASIC FEATURES OF VHDL

•      Concurrency.

-          VHDL is a concurrent language. HDL differs with Software languages with respect to Concurrency only. VHDL executes statements at the same time in parallel, as in Hardware.

•      Supports Sequential Statements.

•      Supports for Test & Simulation.

•      Supports Hierarchies.

•      Supports for Vendor Defined Libraries.

•      Supports Multivalued Logic.

•      Technology/Vendor Independent

•      Portable

•      Reusable

VHDL Benefits

1. Public Standard
2. Technology and Process Independent

–     Includes  technology via libraries

3. Supports a variety of design methodologies

–     Behavioral modeling

–     Dataflow or RTL (Register Transfer Language) Modeling

–     Structural or gate level modeling

4. Supports Design Exchange

–     VHDL Code can run on a variety of systems

5. Supports Design Reuse

–     Code “objects” can be used in multiple designs

6. Supports Design Hierarchy

–     Design can be implemented as interconnected submodules

7. Supports Synchronous and Asynchronous Designs
8. Supports Design Simulation

–     Functional (unit delay)

–     Timing (“actual” delay)

9. Supports Design Synthesis

–     Hardware implementation of the design obtained directly from VHDL code.

10. Supports Design Documentation

VHDL Limitation

Design of analog circuits and systems is not possible in VHDL. i.e. one can only design digital hardware in VHDL.

VHDL Fundamentals

Like any programming language VHDL also has some basic language fundamentals like identifiers, line termination etc. and rules for them are:

•      VHDL is not case sensitive.

Identifiers

•      Identifiers are used to name items in a VHDL model.

•      A basic identifier may contain only ‘A’ - ’Z’ , ‘a’ - ’z’, ‘0’ - ’9’, and underscore character ‘_’

•      Must start with an alphabet.

•      May not end with an underscore character.

•      Must not include two successive underscore characters.

•      Reserved word cannot be used as identifiers.

Statement Terminator

Each VHDL Statements is terminated using a semicolon

               ;

Comment Operator

To include a comment in VHDL, use the comment operator, which is double hyphen(--).

      --  This is a comment

   --  This is an example of a comment

    y <= 0;  -- can occur at any point

Signal Assignment Operator

To assign a value to a signal data object in VHDL, we use the

signal assignment operator

               <=

Example:

                           y <= ‘1’;    -- signal y is assigned the value ONE

                           z <= a and b;

VHDL Example - Hardware           

•      It is important to remember that VHDL is a “hardware” language, so you must think in term of hardware to write any code.

Consider the following logic circuit to be implemented in VHDL.

To do this one can write the code in 3 different ways,

-- Code Fragment  A

-- y can be calculated as

      y1 <= a and b;

      y2 <= c and d;

      y   <= y1 or y2;

 

--  Code Fragment B

     y   <= y1 or y2;

      y2 <= c and d;

      y1 <= a and b;

-- Code Fragment C

      y2 <= c and d;

       y   <= y1 or y2;

       y1 <= a and b;

All three code fragments produce the same result as it is a concurrent language.

With this introduction let us move towards the code structure.

VHDL Design Units

VHDL provides different types of primary constructs, called Design Units .These are

•      Library Declaration

•      Entity Declaration

–     Describes external view of the design (e.g. I/O)

•      Architecture Body (AB)

–     Describes internal view of the design

•      Configuration Declaration

•      Package Declaration

•      Package Body

Out of these first 3 are mandatory in a complete VHDL code and rests are programmer and requirement dependent. As in a C code, header file and main() is mandatory in a complete C code and others(like functions, structures etc.) are programmer dependent. Now let us discuss each.

Library Declarations – Syntax

LIBRARY  library_name;

USE library_name.package_name.package_parts;

Eg:                  LIBRARY ieee;

USE ieee.std_logic_1164.all;

Package Std_Logic_1164 is specified in the library IEEE.

The library IEEE clause must be used in design units, which will use this package.

IEEE Packages

•         std_logic_1164

•         std_logic_misc

•         std_logic_components

•         std_logic_textio

•         std_logic_arith

•         std_logic_unsigned

•         std_logic_signed

 Basic Structure of a VHDL File

•      Entity

–     Entity declaration: interface to outside world; defines input and output signals. (for example if one wants to design a two input AND gate then the interface to the outside world will be its two input and one output)

– Architecture: describes the entity, contains processes, components operating concurrently. (means it contains the information of what is the relation between the input and output)

Entity Declaration

Entity Declaration describes the interface of the component, i.e. input and output ports.

Entity Declaration –Syntax

entity NAME_OF_ENTITY is

            port (signal_names: mode type;

                     signal_names: mode type;

                                    :

                  signal_names: mode type);

end [NAME_OF_ENTITY] ;

•      NAME_OF_ENTITY: user defined

•      signal_names: list of signals (both input and output)

•      mode: in, out, buffer, inout

•      type(data type): boolean, integer, character, std_logic  (will be discussed later)

eg: entity of a two input AND gate will be:

Similarly entity and library declaration of a three input xor gate will be:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY xor3 IS
             PORT(
                         A : IN STD_LOGIC;
                         B : IN STD_LOGIC;
                         C : IN STD_LOGIC;
                         Result : OUT STD_LOGIC
                  );
END xor3;

Eg: entity declaration of a logic circuit having inputs ‘a’, ‘b’ and ‘c’ single bit and ‘s’ as two bit wide and having outputs ‘e’ and ‘f’ single bit and ‘y’ as five bit wide will be,

Entity my_example is

 port( a,b,c: in std_logic;

                    s: in std_logic_vector(1 downto 0);
              e,f: out std_logic;
                y: out std_logic_vector(4 downto 0));

 end entity my_example;

The expected RTL view will be: 

 VHDL Standard Data Types: 

Type	Range of values	Example declaration
integer	implementation defined	signal index: integer:= 0;
real	implementation defined	variable val: real:= 1.0;
boolean	(TRUE, FALSE)	variable test: boolean:=TRUE;
character	defined in package STANDARD	variable term: character:= ‘@’;
bit	0, 1	signal In1: bit:= ‘0’;
bit_vector	array with each element of type bit	variable PC: bit_vector(31 downto 0)
time	implementation defined	variable delay: time:= 25 ns;
string	array with each element of type character	variable name : string(1 to 10) := “model name”;
natural	0 to the maximum integer value in the implementation	variable index: natural:= 0;
positive	1 to the maximum integer value in the implementation	variable index: positive:= 1;
std_logic/ Std_logic_vector	'U',‘0’,’1’,’X’,’Z’,’W’,’L’,’H’,’-’	signal abc: std_logic

STD_LOGIC type demystified

Value	Meaning
'U'	Uninitialized
‘X’	Forcing (Strong driven) Unknown
‘0’	Forcing (Strong driven) 0
‘1’	Forcing (Strong driven) 1
‘Z’	High Impedance
‘W’	Weak (Weakly driven) Unknown
‘L’	Weak (Weakly driven) 0. Models a pull down.
‘H’	Weak (Weakly driven) 1.  Models a pull up.
‘-’	Don't Care

BIT versus STD_LOGIC

•      BIT type can only have a value of ‘0’ or ‘1’

•      STD_LOGIC can have nine values

–     'U',‘0’,’1’,’X’,’Z’,’W’,’L’,’H’,’-’

–     Useful mainly for simulation

–     ‘0’,’1’, and ‘Z’ are synthesizable

Port Mode IN

Port Mode OUT

Port Mode INOUT

Port Mode BUFFER

ARCHITECTURE

•      Architecture defines the functionality of the entity.

•      It forms the body of the VHDL code.

•      Architecture belongs to a specific entity.

•      Various constructs are used in the description of the architecture.

Syntax

architecture architecture_name of NAME_OF_ENTITY is

          -- Declarations

              …..   

              …..

begin

            -- Statements

end architecture_name;

eg: architecture body of a two input AND gate having ‘a’, ‘b’ as i/p and ‘z’ as o/p will be

ARCHITECTURE model OF and_gate IS

BEGIN

            z <= a AND b;

END model;

And the complete VHDL code for two input AND gate will be

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY and_gate IS

            PORT(

                        a   : IN STD_LOGIC;

                        b   : IN STD_LOGIC;

                        z   : OUT STD_LOGIC);

END nand_gate;

ARCHITECTURE model OF and_gate IS

BEGIN

            z <= a AND b;

END model;

This is our first VHDL program. It simply performs the anding of signals ‘a’ and ‘b’ and assign the result in ‘z’ as appeared in the code. But as discussed earlier, while working with the VHDL, one needs to think about hardware, in this sense this code actually creates an AND gate with ‘a’ and ‘b’ as its two inputs and ‘z’ as its output.

Now if you understand all of this then let us pause the programming concepts and try our hands on XILINX. I am working with XILINX12.3 and going to explain all this with the help of below mentioned steps. You can download this from:
http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/archive.html just create your account and download it. Or you can contact me for the same.

1.   Open Xilinx
  ·  After installation a desktop icon named “Xilinx ISE Design Suite 12.3” is created. You just need to double click on it and “ISE Project Navigator” will open up, like this

2.  Now go to file and click on “New Project”

3. The “New Project Wizard” will open up. Here you can,
    ·  Mention the name of your project.
   ·  Select the location and work directory (both are same)-it is recommended to create a folder in any of your drive and select that folder for this. Here I am using “F:\xilinx lab”.

4. Now just give your project a name (“andgate” for example) and click on next.

5. “Project Settings” will be displayed. In which Product Category, Family, Device, Package and Speed are your FPGA Device’s specification (refer to the FPGA kit you are using). Use default if you need to work with simulator only. For rest select as shown in the figure. And click on next.

6. This shows the project summary. Just click on finish.

7. After clicking on finish a project, with the given name and at specified location, is creates and extension is .xise. Check the figure. If not then you have done something wrong and you need to repeat the above six steps again correctly.

8.  Now go to “Project” and click on “New Source”

9.  This will open the “New Source Wizard”. Here click on “VHDL Module” and then write the “file Name” which is the Module name. This will be the entity name you need to create.

10.  Just write the “File Name”(i.e. entity name) and click on “Next”

11.  The “Define Module” will define the interface to the module i.e. entity. This actually creates the entity, which we have discussed earlier.

12. Provide the required no of interface here with their type. Click on “in” to change the direction from “in” to “out”. Then click on “Next”. Do not panic if you made and mistake here because you can change this in the program also.

13. This shows the summary of the new source. Just click on the finish.

14.   After clicking on the “Finish” the module is created and added to the project.

      A raw VHDL code is also created having library, entity and outline for architecture as shown below. If this is not happening you may have done something wrong. I just copy this code and past it here for your reference.

    ----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date:    17:45:59 02/07/2016

-- Design Name:

-- Module Name:    andgate - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity andgate is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           z : out  STD_LOGIC);

end andgate;

architecture Behavioral of andgate is

begin

end Behavioral;

15.  Now you just need to write your code in between begin and end architecture. Which is:

Z<= a and b;

As shown in this figure and save your code.

Congratulations your first VHDL code is now complete.